The present invention relates to a dynamic RAM (Random Access Memory) device.
Recent dynamic RAM devices have commonly employed what is termed a "static column" mode to increase the read-out speed and reduce the cycle time of the device. To realize this mode, a columnar arrangement of static circuits is employed, similarly to a static RAM device, which makes it unnecessary to provide a precharge circuit as in the case of other dynamic RAM devices. That is, each input/output line is pulled up to a predetermined potential through an input/output load by a supply potential V.sub.cc so that it cannot be swung within the full range from ground potential to V.sub.cc. As a result, it is possible to make the column decoder a static-type decoder.
FIG. 1 is a circuit diagram of a typical D-RAM (Dynamic Random Access Memory) device. The D-RAM includes a plurality of memory cells, pairs of bit lines, word lines, sense amplifier circuits, a pair of input/output lines, etc. In FIG. 1, each memory cell includes one N-type MOS (Metal Oxide Semiconductor) translator 4 and one charge storage device 12 such as a capacitor. The transistor 4 is connected between a respective bit line BL or /BL ("/" denoting negation, i.e., the complementary form of the signal, as shown in the drawings by the more conventional bars over the signal designations) and one electrode of the charge storage device 12. The gate electrode of the transistor 4 is connected to a corresponding word line WL. The other electrode of the charge storage device is grounded.
Each sense amplifier circuit 16 has two driver N-type MOS transistors 5 and 6 and two load P-type MOS transistors 2 and 3. A first driver transistor 5 is connected between the bit line BL and a first common node 16a, and a gate electrode of the transistor 5 is connected to the other bit line /BL. A second driver transistor 6 is connected between the other bit line /BL and the first common node 16a, and a gate electrode thereof is connected to the one bit line BL. A first load transistor 2 is connected to the bit line BL. A first load transistor 2 is connected between the bit line BL and a second common node 16b, and a gate electrode thereof is connected to the other bit line /BL. A second load transistor 3 is connected between the bit line /BL and the second common node 16b, and the gate electrode thereof is connected to the bit line BL.
A first enable N-type MOS transistor 7 is connected between the first common node 16a and ground, and a gate electrode thereof receives a first enable signal S.sub.0. A second enable P-type MOS transistor 1 is connected between the second common node 16b and a supply potential node, and a gate electrode thereof receives a second enable signal /S.sub.0.
An equalizer circuit 14 is coupled between the two bit lines BL and /BL for equalizing the potential between the two lines prior to information stored in the memory cell being read out when the cell is selected for read out. The equalizer circuit is implemented with an N-type MOS transistor connected between the bit lines BL and /B, a gate electrode thereof receiving an enabling signal.
A first transfer N-type MOS transistor 8 is connected between the bit line BL and the uncomplemented input/output line I/O. The gate electrode of the transistor 8 receives a column signal Y.sub.i generated by a column decoder 15. A second transfer N-type MOS transistor 9 is connected to the complemented bit line /BL and the complemented input/output line /I/O. The gate electrode of this transistor is connected to the gate electrode of the first transistor 8 and receives the column signal Y.sub.i.
An input/output load 13, composed of two N-type MOS transistors 10 and 11, is connected to the two input/output lines I/O and /I/O. The first load transistor 10 is connected between the input/output line I/O and a supply potential node, and the gate electrode thereof is connected to the supply potential node. The second load transistor 11 is connected between the complemented input/output line /I/O and the supply potential node, while the gate electrode of this transistor is connected to the supply potential node.
FIG. 2 shows waveforms in the conventional D-RAM device.
In the operation of this device, it is assumed that the selected memory cell connected to the bit line BL has stored therein a "1" data bit. The potential of the bit lines BL and /BL will be about half the supply potential. The external signal /RAS goes from an "H" (high) level to a "L" (low) level, as shown in waveform (a), at time t.sub.0. Then, at time t.sub.1, the word signal on the selected word line WL goes from "L" to "H", according to the change in /RAS, as shown in waveform (b). As a result, the transistor 4 of the selected memory cell is rendered conductive, and the potential of the bit line BL goes up, as shown in waveform (c). At time t.sub.2, the potential of the first enable signal S.sub.0 goes from "L" to "H" and the potential of /S.sub.0 goes to "L" from "H", as shown in waveforms (d) and (e) in FIG. 2. Thus, the first and second enable transistors 7 and 8 are placed in the conductive state and the sense amplifier is also enabled.
The sense amplifier 16 amplifies the potential between the two bit lines BL and /BL. At this time, the potential of the bit line BL is at the "H" level (V.sub.cc), while the potential on the complemented bit line /BL is an "L" level (ground), as shown in waveform (c). At time t.sub.3, the column signal Y.sub.i from the column decoder 15 goes high, as seen in waveform (f), and the first and second transfer transistors 8 and 9 are rendered conductive. Accordingly, the potential of the bit lines BL and /BL is transferred to the input/output lines I/O and /I/O, respectively. That is, the potential of I/O is the "H" level and the potential of /I/O is an intermediate level, as shown in waveform (g).
Because current flows from the supply potential node to ground through the input/output load transistor 11, the input/output line /I/O, and the second transfer transistor 9, the bit line /BL, the second driver transistor 6, the first common node 16a, and the first enable transistor 7, and the drive capacities of the load transistors 10 and 11 and the drive transistors 5 and 6 are substantially the same, the potential of the input/output line /I/O will not swing by the full potential difference between V.sub.cc and ground. That is, the potential of the bit line /BL is limited to the intermediate potential V.sub.m, which is less than half the supply potential V.sub.cc, as indicated in waveform (c).
At time t.sub.4, the external signal /RAS goes high, as seen in waveform (a). The word signal WL and the column signal Y, go to the "L" level from the "H" level following the /RAS signal, as shown in waveforms (b) and (f). As a result, the transistor 4 of the selected memory cell and the transfer transistors 8 and 9 are rendered nonconductive. The input/output line /I/O goes up to the supply potential, as shown in waveform (g). At time t.sub.5, the first enable signal S.sub.0 goes down to the "L" level from the "H" level following the change in the external signal /RAS, while the second enable signal S.sub.0 makes the opposite transition, as shown in waveforms (d) and (e), and the first and second enable transistors 7 and 1 are nonconductive. As a result, the sense amplifier 16 is disabled. Subsequently, the equalizer circuit 14 is enabled, and the potentials of the two bit lines BL and /BL are made the same.
In the case where the selected memory cell has stored therein a "0" data bit, the operation is the same as described above, except that the potentials of the bit lines BL and /BL will be as shown in waveform (c').
In the D-RAM device constructed and operated as described above, when a "0" data bit is stored in the memory cell, the intermediate potential V.sub.m will remain on the charge storage device at the completion of the read-out operation. As a result, during the following read-out operation, incorrect information can be read out.